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CY28400
100-MHz Differential Buffer for PCI Express and SATA
Features
* CK409 or CK410 companion buffer * Four differential 0.7V clock pairs * Individual OE controls * Low CTC jitter (< 50 ps) * Programmable bandwidth * SRC_STOP# power management control * SMBus Block/Byte/Word Read and Write support * 3.3V operation * PLL Bypass-configurable * Divide by 2 programmable outputs * 28-pin SSOP package
Functional Description
The CY28400 is a differential buffer and serves as a companion device to the CK409 or CK410 clock generator. The device is capable of distributing the Serial Reference Clock (SRC) in PCI Express and SATA implementations.
Block Diagram
Pin Configuration
DIFT1 OE_(1,6) SRC_STOP# PWRDWN#
Output Control
DIFC1
DIFT2 SCLK SDATA
SMBus Controller Output Buffer
DIFC2
PLL/BYPASS# SRCT_IN SRCC_IN
DIFT5 DIFC5
VDD SRCT_IN SRCC_IN VSS VDD DIFT1 DIFC1 OE_1 DIFT2 DIFC2 VDD PLL/BYPASS# SCLK SDATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27
26
25 24 23 22 21 20 19 18 17 16 15
VDD_A VSS_A IREF VSS VDD DIFT6 DIFC6 0E_6 DIFT5 DIFC5 VDD HIGH_BW# SRC_STOP# PWRDWN#
28 SSOP
DIV
HIGH_BW# DIFT6 DIFC6
CY28400
PLL
Cypress Semiconductor Corporation Document #: 38-07591 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised June 1, 2005
CY28400
Pin Descriptions
Pin 2,3 6,7,9,10,19,20,22,23 8,21 Name SRCT_IN, SRCC_IN DIFT/C(2:1) & (6:5) OE_1, OE_6 Type I,DIF O,DIF I,SE Description 0.7V differential SRC inputs from the clock synthesizer 0.7V differential clock outputs 3.3V LVTTL active LOW input for three-stating differential outputs (DIFT2 and DIFT5 are unaffected by the assertion of OE inputs) 3.3V LVTTL input for selecting PLL bandwidth 3.3V LVTTL input for SRC_STOP#, active LOW 3.3V LVTTL input for Power Down, active LOW SMBus slave clock input Open collector SMBus data A precision resistor is attached to this pin to set the differential output current 3.3V LVTTL input for selecting fan-out or PLL operation 3.3V power supply for PLL Ground for PLL Ground for outputs 3.3V power supply for outputs
17 16 15 13 14 26 12 28 27 4,25 1,5,11,18,24
HIGH_BW# SRC_STOP# PWRDWN# SCLK SDATA IREF PLL/BYPASS# VDD_A VSS_A VSS VDD
I,SE I,SE I,SE I,SE I/O,OC I I 3.3V GND 3.3V GND
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11011100 (DCh).
Table 1. Command Code Definition Bit 7 (6:0) 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Description
Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Description Bit 1 2:8 9 10 11:18 19 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Block Read Protocol Description
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CY28400
Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 20:27 28 29:36 37 38:45 46 .... .... .... .... Description Byte Count from master - 8 bits Acknowledge from slave Data byte 0 from master - 8 bits Acknowledge from slave Data byte 1 from master - 8 bits Acknowledge from slave Data bytes from master/Acknowledge Data Byte N - 8 bits Acknowledge from slave Stop Bit 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Acknowledge from master Stop Byte Read Protocol Description Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge from host Data byte 0 from slave - 8 bits Acknowledge from host Data byte 1 from slave - 8 bits Acknowledge from host Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Acknowledge from host Stop Block Read Protocol Description
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Byte 0: Control Register 0 Bit 7 6 5 4 3 2 @Pup 0 0 0 0 0 1 HIGH_BW# Name Description PWRDWN# drive mode 0 = Driven when stopped, 1 = Three-state SRC_STOP# drive mode 0 = Driven when stopped, 1 = Three-state Reserved Reserved Reserved HIGH_BW# 0 = High Bandwidth, 1 = Low bandwidth Page 3 of 13
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CY28400
Byte 0: Control Register 0 (continued) Bit 1 0 @Pup 1 1 Name PLL/Bypass# Description PLL/Bypass# 0 = Fanout buffer, 1 = PLL mode SRC_DIV/2 0 = Divided by 2 mode,1 = Normal (output = input)
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 DIFT/C2 DIFT/C1 DIFT/C6 DIFT/C5 Name Reserved DIFT/C6 Output Enable 0 = Disabled (three-state), 1 = Enabled DIFT/C5 Output Enable 0 = Disabled (three-state), 1 = Enabled Reserved Reserved DIFT/C2 Output Enable 0 = Disabled (three-state), 1 = Enabled DIFT/C1 Output Enable 0 = Disabled (three-state), 1 = Enabled Reserved Description
Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved Allow Control DIFT/C6 with assertion of SRC_STOP# 0 = Free-running, 1 = Stopped with SRC_STOP# Allow Control DIFT/C5 with assertion of SRC_STOP# 0 = Free-running, 1 = Stopped with SRC_STOP# Reserved Reserved Allow Control DIFT/C2 with assertion of SRC_STOP# 0 = Free-running, 1 = Stopped with SRC_STOP# Allow Control DIFT/C1 with assertion of SRC_STOP# 0 = Free-running, 1 = Stopped with SRC_STOP# Reserved Description
Byte 3: Control Register 3 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
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CY28400
Byte 4: Vendor ID Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
Byte 5: Control Register 5 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved meet all AC and DC parameters. This means no glitches, frequency shifting or amplitude abnormalities among others. Description
PWRDWN# Clarification[1]
The PWRDWN# pin is used to shut off all clocks cleanly and instruct the device to evoke power savings mode. Additionally, PWRDWN# should be asserted prior to shutting off the input clock or power to ensure all clocks shut down in a glitch-free manner. PWRDWN# is an asynchronous active LOW input. This signal is synchronized internal to the device prior to powering down the clock buffer. PWRDWN# is an asynchronous input for powering up the system. When PWRDWN# is asserted LOW, all clocks will be held HIGH or three-stated (depending on the state of the control register drive mode and OE bits) prior to turning off the VCO. All clocks will start and stop without any abnormal behavior and must
PWRDWN#--Assertion
When PWRDWN# is sampled LOW by two consecutive rising edges of DIFC, all DIFT outputs will be held HIGH or three-stated (depending on the state of the control register drive mode and OE bits) on the next DIFC HIGH-to-LOW transition. When the SMBus power-down drive mode bit is programmed to `0', all clock outputs will be held with the DIFT pin driven HIGH at 2 x Iref and DIFC three-state. However, if the control register PWRDWN# drive mode bit is programmed to `1', then both DIFT and the DIFC are three-stated.
PWRDWN# DIFT DIFC
Figure 1. PWRDWN# Assertion Diagram
Note: 1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN# is an undefined mode and not recommended. Operation in this mode may result in glitches excessive frequency shifting.
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CY28400
PWRDWN#--Deassertion
The power-up latency is less than 1 ms. This is the time from the deassertion of the PWRDWN# pin or the ramping of the power supply or the time from valid SRC_IN input clocks until the time that stable clocks are output from the buffer chip (PLL locked). If the control register PWRDWN# three-state bit is programmed to `1', all differential outputs will be driven HIGH in less than 300 s of PWRDWN# deassertion to a voltage greater than 200 mV.
Tstable <1mS
PWRDWN# DIFT DIFC
Tdrive_Pwrdwn# <300uS, >200mV
Figure 2. PWRDWN# Deassertion Diagram Table 4. Buffer Power-up State Machine State 0 1 2[3] 3[2] 3.3V Buffer power off After 3.3V supply is detected to rise above 1.8V-2.0V, the buffer enters state 1 and initiates a 0.2-ms-0.3-ms delay Buffer waits for a valid clock on the SRC_IN input and PWRDWN# deassertion Once the PLL is locked to the SRC_IN input clock, the buffer enters state 3 and enables outputs for normal operation
No Input Clock
Description
S2 S1
Delay >0.25ms
Wait for Input Clock & PWRDWN# Deassertion
PWRDWN# Asserted
S0
Power Off
S3
Normal Operation
Figure 3. Buffer Power-up State Diagram
Notes: 2. The total power-up latency from power on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input). 3. If power is valid and PWRDWN# is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid input clocks are detected, valid power, PWRDWN# deasserted with the PLL locked and stable are the DIF outputs enabled.
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CY28400
SRC_STOP# Clarification
The SRC_STOP# signal is an active LOW input used for clean stopping and starting the DIF outputs (valid clock must be present on SRCT_IN). The SRC_STOP# signal is a de-bounced signal in that it's state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) Table 5. SRC_STOP# Functionality[4] SRC_STOP# 1 0 DIFT Normal Iref * 6 or Float DIFC Normal Low the control register SRC_STOP# three-state bit is programmed to `0', the final state of all stopped DIFT/C signals is DIFT clock = HIGH and DIFC = LOW. There is to be no change to the output drive current values, DIFT will be driven HIGH with a current value equal 6 x Iref, and DIFC will not be driven. When the control register SRC_STOP# three-state bit is programmed to `1', the final state of all stopped DIF signals is LOW, both DIFT clock and DIFC clock outputs will not be driven.
SRC_STOP# Deassertion
All differential outputs that were stopped will resume normal operation in a glitch-free manner. The maximum latency from the deassertion to active outputs is between 2-6 DIFT/C clock periods (two clocks are shown) with all DIFT/C outputs resuming simultaneously. If the control register three-state bit is programmed to `1' (three-state), then all stopped DIFT outputs will be driven high within 10 ns of SRC_STOP# deassertion to a voltage greater than 200 mV.
SRC_STOP# Assertion
The impact of asserting the SRC_STOP# pin is all DIF outputs that are set in the control registers to stoppable via assertion of SRC_STOP# are stopped after their next transition. When
1mS SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable)
Figure 4. SRC_STOP# = Driven, PWRDWN# = Driven
1mS SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable)
Figure 5. SRC_STOP# =Driven, PWRDWN# = Three-state
Note: 4. In the case where OE is asserted HIGH, the output will always be three-stated regardless of SRC_STOP# drive mode register bit state.
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CY28400
1mS SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable)
Figure 6. SRC_STOP# = Three-state, PWRDWN# = Driven
1mS SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable)
Figure 7. SRC_STOP# = Three-state, PWRDWN# = Three-state
Output Enable Clarification
The outputs may be disabled in two ways, via writing a `0' to the SMBus register bit corresponding to output of interest or by asserting an OE input pin LOW. In both methods, if SMBus registered bit has been written LOW or the OE pin is LOW or both, the output of interest will be three-stated. The assertion and deassertion of this signal is asynchronous. Table 6. OE Functionality OE (Pin) 1 1 0 0 OE (SMBus Bit) 1 0 1 0 DIFT Normal Three-state Three-state Three-state DIFC Normal Three-state Three-state Three-state
SRC_DIV2# Assertion
The impact of writing a `0' to the SRC_DIV/2 register bit is that all DIF outputs will transition cleanly in a glitch-free manner from normal operation (output frequency equal to input) to half the input frequency within 2-6 DIF clock periods.
SRC_DIV2# Deassertion
The impact of writing a `0' to the SRC_DIV/2 register bit is that all DIF outputs will transition cleanly in a glitch-free manner from divide by 2 mode to normal (output frequency is equal to the input frequency) operation within 2-6 DIF clock periods.
PLL/BYPASS# Clarification
The PLL/Bypass# input is used to select between bypass mode (no PLL) and PLL mode. In bypass mode, the input clock is passed directly to the output stage resulting in 50 ps additive jitter (50 ps + input jitter) on DIF outputs. In the case of PLL mode, the input clock is pass through a PLL to reduce high-frequency jitter. The BYPASS# mode may be selected in two ways, via writing a `0' to SMBus register bit or by asserting the PLL/BYPASS# pin LOW. In both methods, if the SMBus register bit has been written low or PLL/BYPASS# pin is LOW or both, the device will be configure for BYPASS operation.
OE Assertion (Transition from `0' to `1')
All differential outputs that were three-stated will resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2-6 DIF clock periods. In addition, DIFT clocks will be driven HIGH within 10 ns of OE assertion to a voltage greater than 200 mV.
OE Deassertion (Transition from `1' to `0')
The impact of deasserting OE is that each corresponding output will transition from normal operation to three-state in a glitch-free manner. The maximum latency from the deassertion to three-stated outputs is between 2-6 DIF clock periods.
HIGH_BW# Clarification
The HIGH_BW# input is used to set the PLL bandwidth. This mode is intended to minimize PLL peaking when two or more buffers are cascaded by staggering device bandwidths. The PLL low-bandwidth mode may be selected in two ways, via writing a `0' to SMBus register bit or by asserting the HIGH_BW# pin is LOW or both, the device will be configured for low-bandwidth operation.
SRC_DIV2# Clarification
The SRC_DIV2# feature is used to configure the DIF output mode to be equal to the SRCT_IN input frequency or half the input frequency in a glitch-free manner. The SRC_DIV2# function may be implemented by writing a `0' to SMBus register bit. Document #: 38-07591 Rev. *A
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CY28400
Absolute Maximum Conditions
Parameter VDD VDD_A VIN TS TA TJ OJC OJA ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to VSS Non-functional Functional Functional Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - - - 2000 V-0 1 Max. 4.6 4.6 VDD + 0.5 150 70 150 TBD TBD - Unit V V VDC C C C C/W C/W V
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter VILI2C VIHI2C VIL VIH IIL IIH IOZ CIN COUT LIN IDD3.3V IPD3.3V IPD3.3V Description 3.3 5% SDATA, SCLK SDATA, SCLK Input Low Voltage Input High Voltage 3.3V Input Low Voltage 3.3V Input High Voltage Input Low Leakage Current Input High Leakage Current High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Dynamic Supply Current Power-down Supply Current Power-down Supply Current At max. load and 100 MHz per Figure 8 PD asserted, Outputs driven PD asserted, Outputs Three-stated Except internal pull-up resistors, 0 < VIN < VDD Except internal pull-down resistors, 0 < VIN < VDD -10 2 3 - - - - Condition Min. 3.135 - 2.2 VSS - 0.5 2.0 -5 5 10 5 6 7 215 40 5 Max. 3.465 1.0 - 0.8 VDD + 0.5 Unit V V V V V A A A pF pF nH mA mA mA VDD_A, VDD 3.3V Operating Voltage
AC Electrical Specification
Parameter TDC TSKEW TPERIOD TCCJ TR / TF TRFM TR TF VHIGH VLOW VOX Description DIFT and DIFC Duty Cycle Average Period DIFT/C Cycle to Cycle Jitter DIFT and DIFC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Measured SE Measured SE Condition DIF at 0.7V Measured at crossing point VOX Measured at crossing point VOX at 100 MHz Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Min. 45 - 9.9970 - 175 - - - 660 -150 250 Max. 55 150 10.0533 50 700 20 125 125 850 - 550 Unit % ps ns ps ps % ps ps mv mv mv
Any DIFT/C to DIFT/C Clock Skew, SSC Measured at crossing point VOX
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CY28400
AC Electrical Specification (continued)
Parameter VOX VOVS VUDS VRB tPD(PLL) Description Vcross Variation over all edges Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage Input to output skew in PLL mode Measured SE Measured at crossing point VOX Condition Min. - - - 0.2 - 2.5 Max. 140 VHIGH + 0.3 -0.3 N/A 250 6.5 Unit mV V V V ps ns
tPD(NONPLL) Input to output skew in Non - PLL mode Measured at crossing point VOX
33 4 9 .9 33 4 9 .9
D IF T
T PCB
M e a s u re m e n t P o in t
2pF
D IF C IR E F
475
T PCB
M e a s u re m e n t P o in t
2pF
T r a c e Im p e d a n c e M e a s u r e d D if f e r e n tia lly
Figure 8. Differential Clock Termination
Switching Waveforms
TRise (CLOCK) VOH = 0.525V
CL O
CK
CK #
O CL
VCROSS
VOL = 0.175V
TFall (CLOCK)
Figure 9. Single-Ended Measurement Points for TRise and TFall
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CY28400
V OVS
V RB
V RB V LOW V UDS
Figure 10. Single-ended Measurement Points for VOVS,VUDS and VRB
TPERIOD
Skew Management Point
High Duty Cycle %
Low Duty Cycle %
0.000V
Figure 11. Differential (Clock-CLock#) Measurement Points (Tperiod, Duty Cycle and Jitter)
Ordering Information
Ordering Code CY28400OC CY28400OCT Lead-free CY28400OXC CY28400OXCT 28-pin SSOP 28-pin SSOP (Tape & Reel) Commercial, 0C to 70 C Commercial, 0C to 70 C 28-pin SSOP 28-pin SSOP (Tape & Reel) Package Type Operating Range Commercial, 0C to 70 C Commercial, 0C to 70 C
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CY28400
Package Drawing and Dimensions
28-Lead (5.3 mm) Shrunk Small Outline Package O28
51-85079-*C
All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY28400
Document History Page
Document Title: CY28400 100-MHz Differential Buffer for PCI Express and SATA Document Number: 38-07591 Rev. ** *A ECN No. 130190 375174 Issue Date 11/26/03 See ECN Orig. of Change RGL RGL New Data Sheet Added Lead-free devices Description of Change
Document #: 38-07591 Rev. *A
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